This invention pertains to apparatus and methods for designing and laying out multi-layer circuit substrates, such as multi-layer printed circuit boards (“PCBs”).
PCBs are widely used as circuit substrates for mechanically mounting electrical components and for electrically interconnecting the mounted electrical components. PCBs typically include one or more layers of an insulating substrate (such as fiberglass). During PCB manufacture, a metal layer is deposited on a surface of a substrate layer, and the metal layer is then chemically etched to form a pattern of conductors (or “traces”) on the substrate surface. Multiple substrate/metal layers may be sandwiched together to form a multi-layer PCB.
To interconnect traces between the layers, and to provide a means for attaching electrical components to the PCB, “vias” are formed by drilling holes through the various metal and substrate layers. The holes are typically cylindrically shaped channels formed perpendicular to the PCB substrate surface. The holes are subsequently filled with an electrically conducting material (e.g., solder) to form a low resistance electrical connection between the various layers along the length of the via. A via typically includes a cylindrically-shaped pad on each of the PCB's top and bottom layers and one or more intermediate layers.
PCBs typically are designed using specialized computer aided design (“CAD”) software programs, such as Allegro PCB Design, by Cadence Design Systems, San Jose, Calif. PCB CAD software programs typically include layout tools for specifying the placement and routing of the various traces, electrical  components and vias on a PCB. The layout tools typically perform design rule verification functions to assure that the layout complies with design rules specifying various parameters such as minimum trace-to-trace separations and other parameters. Once a PCB board layout is complete, the PCB CAD software program may be used to generate a “Gerber file” that defines the PCB layout definition. A PCB manufacturer may then use the Gerber file to fabricate PCBs in accordance with the design specified in the Gerber file.
PCB CAD software programs typically include a “via definition” that defines the physical dimensions of the vias that are used in the PCB design. The programs typically utilize a single static via definition for each PCB design—that is, all vias have the exact same geometrical dimensions. Further, the via definition typically includes a pad on each layer of the PCB, including each intermediate layer. Thus, PCB CAD software programs typically generate PCB designs that specify vias having pads on the top and bottom layers and on all intermediate layers.
PCB board manufacturers, however, prefer to remove intermediate pads that are not connected to any traces. In particular, removing such unused intermediate pads minimizes cost and increases reliability by decreasing stray capacitance and reducing manufacturing defects such as short circuits. Some manufacturers use software that scans Gerber files to identify such unused intermediate pads, and then modifies the files to eliminate the unused intermediate pads. Also, some PCB CAD software programs include an option that removes unused intermediate pads during the process used to generate the Gerber file.
Such “pad stripping” techniques, however, occur only after PCB design is complete. Thus, during the design process, the PCB layout is implemented assuming that all vias include pads on all layers, including all intermediate layers. In this regard, the design rule verification functions enforce design rules (such as the minimum separation between a trace and an adjacent via) based on a pre-pad-stripping geometry. Thus, even if a designer knows that a particular via pad on a particular intermediate layer will be subsequently stripped away during the manufacturing process (and thus a larger area could be used for laying out traces), the PCB CAD software programs prohibit the designer from utilizing such unused real estate. As a result, previously known PCB CAD software programs do not permit efficient PCB layout. 